Phase-locked loop (PLL) has been widely used in many engineering applications. The primary function of the PLL is to generate a clean, unitary signal which is in synchronous with a noisy signal where the amplitude and frequency can change with time. This is required in almost all systems that are interfaced with the ac power grid and are intended to interact with it in an active and controlled manner. This includes grid-connected inverters, rectifier loads, motor drives, and battery chargers. PLL has also been extended to perform secondary tasks such as estimation of signal attributes including the magnitude, frequency, harmonics, sequence components, etc.

PLL is highly efficient and is very popular. The trade-off, however, is that parameter design is not always easy especially for those who do not have sufficient experience. This is due to the fact that PLL is inherently nonlinear, and no well-established and easily accessible rules for tuning the parameters have been developed.

This tutorial describes several conventional PLL blocks, as well as enhanced PLL (ePLL) blocks implemented in PSIM for single-phase and three-phase applications. Simple and straightforward design guidelines to adjust the parameters of each PLL are presented. A simple test circuit is used to show the basic waveforms of the PLL block. Then a grid-connected inverter is used to illustrate how the PLL block is used in a practical application.

**Four types of PLL blocks are presented in this tutorial:**

- PLL: Conventional single-phase PLL blocks
- ePLL: Enhanced PLL blocks
- 3-phase PLL: Conventional 3-phase PLL blocks
- 3-phase ePLL: Enhanced 3-phase PLL blocks

Each block comes in two versions: continuous time domain and discrete time domain.

Single-phase PLL has a very simple yet robust structure. However, due to the presence of large double-frequency ripples, it is not suitable for applications that require high level of accuracy. This section presents the PLL and introduces an effective way of tuning its parameters.

The block diagram of the PLL, with the definitions of signals, is shown below.

where

*u(t)* = input signal to the PLL

*ωo* = rated frequency of the input

*y(t)* = unitary output signal synchronous with the input

*y’(t)* = unitary output signal 90-degree delayed version of y(t)

*Ф* = estimated angle

*ω* = estimated frequency in rad/sec.

*kp* = proportional gain

*ki* = integrating gain

- Commonly, the point marked by x in the diagram above is considered as the estimated frequency. However, in this tutorial we consider the point marked by ω as the estimated frequency. This point offers a more accurate estimate of the frequency with smoother dynamics.
- Information of the rated input magnitude Ao is used to tune the gains.

1) Choose the natural frequency ωn as a small fraction of ωo where ωo is the rated frequency of the input. A typical choice can be:

*ω_n=0.1ω_o*

2) Choose a reasonable value of the damping ratio ζ where 0 ≤ ζ ≤ 1. For example, ζ=0.5.

The selected values above make a good trade-off between the transient time and steady-state ripples.

3) Calculate the parameters kp and ki:

Use the previously selected values and the rated amplitude (peak value) of the input Ao to calculate the parameters.

*k_p=(4ζω_n)/A_o*

*k_i=(2ω_n^2)/A_o*

The poles of the linearized PLL loop are at *-ζω_n±jω_n √(1-ζ^2 ).* Therefore, for a good choice of ζ (e.g. around 0.7), the time-constant of the response is around *τ=1/(ζω_n )*. For example, for* ζ=0.5* and *ω_n=0.1ω_o=0.1*377=37.7 rad/sec*., the time constant is around *τ=1/(0.5*37.7)* which is around 50 ms.

The major drawback of the conventional PLL is the presence of the double-frequency ripples at the output, as explained below. At the point denoted by z in the diagram in Page 2, a double-frequency component with the magnitude of Ao/2 exists due to the multiplication block.

The double-frequency ripples at the point ω will be:

For instance, for a choice of ω_n/ω_o =0.1, the error is 0.5% of ωo (or 0.005 pu). For a 60-Hz system, this is equal to 300 mHz (600 mHz peak-to-peak).

The double-frequency ripples at the point Ф will be:

For instance, for a choice of *ω_n/ω_o =0.1*, the error is equal to* 6ζ deg. For ζ=0.5*, the error of the phase angle is around 3o (6o peak-to-peak).

The analysis above shows that the transient time is inversely proportional to ζωn where the angle ripple is directly proportional to ζωn. For the recommended values of *ω_n=0.1ω_o* and* ζ=0.5*, the time constant is around 50 ms and the angle ripple is around 6o peak-to-peak.

Two blocks for conventional PLL, one in the continuous time domain and the other in the discrete time domain, are provided in PSIM as below:

The PLL block in the discrete domain (right) has the same image and terminal definition as the block in the continuous domain (left), except there, is a character “z” at the upper right corner.

**The PLL block parameters are:**

Proportional Gain *kp* = Proportional gain in the PLL circuit

Integral Gain* ki* = Integral gain in the PLL circuit

Rated Input Frequency = Rated frequency of the input, in Hz

Sampling Frequency = Sampling frequency, in Hz (for the discrete domain block only)

A simple circuit is built to test the basic operations of the PLL block as shown below.

The input signal u(t) is generated with various disturbances: phase disturbance at 0.2 sec., frequency change at 0.8 sec., and amplitude change at 0.8 sec. The waveforms are shown below.

The top panel shows the input signal u(t), the unitary synchronous output y(t), and the unitary quadrature output y’(t). The lower panel shows the input signal frequency and the estimated frequency by the PLL.

Waveforms around 0.2 sec. are zoomed in for closer inspection, as shown below.

The following observations can be made from these waveforms:

- There is a steady double-frequency ripple with the peak-to-peak magnitude of about 600 MHz on the frequency and about 6◦ on the phase angle (as expected for the selection of ζ = 0.5 and ωn = 0.1ωo).
- As expected, it takes about 50 ms for the system to approach the new operating point.
- When the magnitude of the input signal is increased, the peak-to-peak frequency error increases almost proportionally.

This simulation clearly confirms why the conventional PLL is not a suitable choice for applications that require fast responses (often below one cycle of 60 Hz or 50 Hz, i.e. 20 ms) and small errors (e.g. below half a degree in phase error and below 10 MHz in frequency error).

A single-phase grid-connected inverter shown below is presented here to illustrate how PLL is used in a practical application. Files of this example can be found in “examples\PLL Blocks\single-phase”.

A proportional-resonant (PR) controller is used to control the inverter current. The transfer function of the PR controller is:

In a control loop with ac commands and disturbances, such as this example, the PR controller has the advantage of removing the steady-state error completely. The feedforward term Vg*y_pll cancels the grid voltage and provides a soft start of the inverter. Here, we assume the grid voltage amplitude Vg is known. In the enhanced PLL, this assumption is no longer needed.

The inverter provides a sinusoidal current at the desired magnitude in phase with the grid voltage vc(t). The PR gain may be designed using the root-locus approach, optimal control theory, or any other approaches (see the section below). The PLL design is provided in the parameter file. This is the same design that was discussed in the previous section: *ζ = 0.5, ωn = 0.1ωo.*

Waveforms of the inverter circuit are shown below.

The current reference magnitude changes from 10 A to 20 A at t=0.075 s and then changes to 5 A at t=0.15 s. The top panel shows the current reference (red), the inverter current (green), and the reference magnitude (blue). The bottom panel shows the grid voltage.

For the sake of comparison, the PLL block is replaced with an ideal synchronization signal generator (which is a unit-magnitude voltage source in synchronous with the grid voltage), and two results are compared as shown below.

It is clearly observed that the inverter responses with the PLL are more distorted. The distortion is more pronounced at the low current magnitude. The distortion may be reduced at the expense of response speed to grid voltage variations.

Similar test circuit and single-phase inverter examples are provided for the discrete domain PLL block, and the PSIM files can be found in “examples\Digital Control\PLL Blocks\single-phase”.

Single-phase enhanced PLL (ePLL) was originally proposed in [1, 2]. Extensive coverage of ePLL can be found in the book [3].

The originality of ePLL is that, without changing the original and widely accepted structure of the conventional PLL, it adds a few simple blocks to remove its main drawback: double-frequency ripple. As a result of this improvement, ePLL also provides an estimate of the signal amplitude, fundamental component, and total distortions.

This section presents ePLL and introduces an effective way of tuning its parameters. Its implementation in PSIM is discussed. A simple test example and an inverter example are presented to illustrate the use of ePLL.

The Block diagram of the EPLL implemented in the continuous time domain is shown below. Definition of the signals are given as follows.

where

u(t) = input signal to the PLL

ωo = rated frequency of the input

y(t) = unitary output signal synchronous with the input

y’(t) = unitary output signal 90-degree delayed version of y(t)

Ao = rated amplitude (peak value) of the input

A = estimated amplitude of the input

Ф = estimated angle

ω = estimated frequency in rad/sec.

yf = estimated fundamental component

kp = proportional gain

ki = integrating gain

ka = amplitude gain

The division block does not exist in conventional structures. As a result, the setting of parameters depends on the amplitude of the input signal. Here, the division block is added to allow tuning of parameters independent of the input signal magnitude. The information of rated magnitude Ao is used only to avoid any possible divide-by-zero in the division block. The constant E is suggested to be 0.001.

1) Choose the first damping ratio ζ1 which determines the filtering strength of the ePLL. A smaller ζ1 means stronger filtering but slower dynamic response. We suggest a value range below for typical power applications:

*0.25 ≤ ζ_1 ≤ 0.75*

2) Choose the second damping ratio ζ2 which corresponds to the damping ratio of the frequency loop. Since very fast frequency variation does not happen typically, can be set to a large value to avoid unnecessary oscillations. The recommended value range is:

*1 ≤ ζ_2 ≤ 2*

3) Choose the constant λ. For typical applications, the suggested range of the constant λ is:

*0 ≤ λ ≤ 20*

This will give the desired trade-off. A larger value of λ means stronger suppression of the frequency swing. The default value is set to 10. If λ=0, this feature is disabled.

4) Set the parameter *kp* and* ka* as:

*k_p=k_a=2ζ_1 ω_o*

5) Determine the integrating gain *ki* as:

*k_i=(k_p^2) / (8ζ_2^2 )*

The integrating gain ki may be made adaptive to further limit the range of frequency oscillations caused by phase angle jump or during the starting process [4]. With this approach, the ki equation is changed to:

If e≠0 then use ε=0.001 and the rest of the parameters to calculate the integration constant.

This will limit the spurious frequency estimation swings caused by phase jump at the cost of reducing the actual frequency estimation speed.

Two blocks for enhanced PLL, one in the continuous time domain and the other in the discrete time domain, are provided in PSIM as below:

The PLL block in the discrete domain (right) has the same image and terminal definition as the block in the continuous domain (left), except there is a character “z” at the upper right corner.

**The ePLL block parameters are:**

Proportional Gain kp = Proportional gain in the PLL circuit

Integral Gain ki = Integral gain in the PLL circuit

Rated Input Frequency = Rated frequency of the input, in Hz

Coefficient lambda = Coefficient λ as defined in the section above

Sampling Frequency = Sampling frequency, in Hz (for the discrete domain block only)

A simulation model is built to test the ePLL block in the basic operating conditions as shown below.

The input signal u(t) is generated with various disturbances: phase disturbance at 0.2 sec., frequency change at 0.8 sec., and amplitude change at 0.8 sec. The waveforms are shown below.

The top panel shows the input signal u(t), the unitary synchronous output y(t), the unitary quadrature output y’(t), and the fundamental output yf(t). The middle panel shows the input signal frequency and the estimated frequency. The lower panel shows the input signal amplitude and the estimated amplitude by the PLL block.

The following observations can be made from these waveforms:

- There is no double-frequency ripple
- There is no steady-state error or offset in any variables. All signal variations are tracked
- The transient response is fast

The absence of the double frequency ripple is the biggest improvement of the enhanced PLL block as compared to the conventional PLL block.

A single-phase grid-connected inverter shown below is presented here to illustrate how the ePLL block is used in a practical application. PSIM files of this example can be found in “examples\PLL Blocks\single-phase”.

A proportional-resonant (PR) controller is used to control the inverter current. The PR controller has the advantage of removing the steady-state error completely. The feedforward term is the fundamental output *yf(t)*, and it cancels the grid voltage and provides a soft start to the inverter. Note that in this case, the grid voltage amplitude information is no longer needed.

The inverter provides a sinusoidal current at the desired magnitude in phase with the grid voltage *vc(t)*. The PLL design is provided in the parameter file. This is the same design that was discussed in the previous section: *ζ1 = 0.5, ζ2 = 1, λ = 10.*

Waveforms of the inverter circuit are shown below.

The current reference magnitude changes from *10 A to 20 A at t=0.075 s* and then changes to* 5 A at t=0.15 s.* The top panel shows the current reference (red), the inverter current (green), and the reference magnitude (blue). The bottom panel shows the grid voltage.

For comparison, the PLL block is replaced with an ideal synchronization signal generator (which is a unit-magnitude voltage source synchronous with the grid voltage), and its result is compared with the result of the enhanced PLL and conventional PLL, as shown below.

The top panel shows the inverter current with the ideal synchronization signal and with ePLL. The bottom panel shows the inverter current with the ideal synchronization signal and with the conventional PLL. It is clearly observed that ePLL offers a very similar result as the ideal synchronization signal with no distortion in the steady state. On the other hand, the waveform of the conventional PLL block is more distorted. The distortion is more pronounced at a low current magnitude. The distortions may be reduced at the expense of response speed to grid voltage variations.

Similar test circuit and single-phase inverter examples are provided for the discrete domain PLL block, and the PSIM files can be found in “examples\Digital Control\PLL Blocks\single-phase”.

The conventional 3-phase PLL does not have the problem of the double-frequency ripple due to the fact that the ripples of the three phases cancel each other. However, when the 3-phase inputs are not balanced, the double-frequency ripple will be present.

The block diagram of the conventional 3-phase PLL, with the definitions of signals, is shown below.

where

*u(t)* = input signal to the PLL

*ωo* = rated frequency of the input

*y(t)* = unitary output signal synchronous with the input

*y’(t)* = unitary output signal 90-degree delayed version of y(t)

*Ф* = estimated angle

*ω* = estimated frequency in rad/sec.

*ud* = d-axis component of the input

*uq* = q-axis component of the input

*uo* = zero-axis component of the input

*kp* = proportional gain

*ki* = integrating gain

The abc/dqo transformation is defined as:

**Remarks**

- Commonly, the point marked by x in the diagram above is considered as the estimated frequency. However, in this tutorial, we consider the point marked by ω as the estimated frequency. This point offers a more accurate estimate of the frequency with smoother dynamics
- The division block does not exist in conventional structures. As a result, the setting of parameters depends on the amplitude of the input signal. Here, we have added the division block to allow tuning of parameters independent of the input signal magnitude. The information of rated magnitude Ao is used only to avoid any possible divide-by-zero in the division block. The constant ϵ is suggested to be 0.001.

1) Choose the natural frequency ωn as a small fraction of ωo:

*0.1≤ω_n/ω_o≤0.5*

2) Choose a reasonable value of the damping ratio:

*0.5≤ ζ ≤1*

These values make a good trade-off between the transient time and filtering strength as explained below.

3) Calculate the parameters kp and ki:

*k_p=2ζω_n*

*k_i=ω_n^2*

The poles of the linearized PLL loop are at *-ζω_n±jω_n √(1-ζ^2 )*. Therefore, for a good choice of ζ (e.g. around 0.7), the time-constant of the response is around *τ=1/(ζω_n )*. For example, for *ζ=0.7 *and* ω_n=0.25ω_o=0.25*377=94.25 rad/sec.*, the time constant is around *τ=1/(0.7*94.25)* which is around 16 ms or one full cycle of 60 Hz.

The 3-phase PLL block does not have the double-frequency ripple problem when the three-phase input is balanced. However, when the input is unbalanced, the double-frequency ripple will be present.

Assume that the amplitudes of the positive-sequence and the negative sequence components of the input are U+ and U- respectively. At point z in the 3-phase PLL diagram, the double-frequency component amplitude is *U^-/U^+* .

The double-frequency ripples at the point ω will be:

For instance, for a choice of ω_n/ω_o =0.25, and the imbalance factor of IF=U^-/U^+ =0.04, this corresponds to 75 MHz (150 MHz) error in a 60-Hz system.

The double-frequency ripples at the point Ф will be:

For instance, for a choice of ω_n/ω_o =0.25, and the imbalance factor of IF=0.04, the error is equal to 6ζ deg. For ζ=0.5, the error of the phase angle is around 0.3o (0.6o peak-to-peak).

The analysis above shows that the transient time is inversely proportional to ζωn where the angle ripple is directly proportional to ζωn. For the recommended values of ω_n=0.25ω_o and ζ=0.5, the time constant is around 21 ms (just over one cycle of the 60-Hz system) and the angle ripple is around 0.6o peak-to-peak.

The integral gain ki may be made adaptive to further limit the range of frequency oscillations caused by phase angle jump or during the starting process. With this approach, the ki equation is changed to:

This will limit the spurious frequency estimation swings caused by phase jump at the cost of reducing the actual frequency estimation speed. For typical applications, the suggested range of the constant λ is:

*0 ≤λ≤20*

This will give the desired trade-off. A larger value of λ means stronger suppression of the frequency swing. The default value is set to 10. If λ=0, this feature is disabled.

Two blocks for enhanced PLL, one in the continuous time domain and the other in the discrete time domain, are provided in PSIM as below:

The PLL block in the discrete domain (right) has the same image and terminal definition as the block in the continuous domain (left), except there, is a character “z” at the upper right corner.

**The PLL block parameters are:**

Proportional Gain *kp* = Proportional gain in the PLL circuit

Integral Gain *ki* = Integral gain in the PLL circuit

Rated Input Frequency = Rated frequency of the input, in Hz

Rated Input Amplitude (peak) = Rated input amplitude *Ao* (phase peak value)

Coefficient lambda = Coefficient λ

Sampling Frequency = Sampling frequency, in Hz (for the discrete domain block only)

A simple circuit is built to test the basic operations of the 3-phase PLL block as shown below.

The 3-phase input signals consist of positive, negative, and zero sequence components generated by three subcircuits. The negative and zero sequence circuits use the phase angle from the positive sequence circuit to ensure the same frequency, and they also have their own initial phase shifts.

**The input signals have the following changes and disturbances:**

- Phase disturbance at 0.1 sec
- Frequency change at 0.3 sec
- Amplitude change at 0.4 sec
- Negative sequence component is applied at 0.5 sec
- Zero sequence component is applied at 0.6 sec

The waveforms are shown below.

The top panel shows the input signal *uabc(t)*. The upper middle panel shows the input *ua(t)* and the unitary synchronous output *y(t)*. The lower middle panel shows the input frequency and the estimated frequency. The bottom panel shows the estimated d-axis, q-axis, and zero-axis components of the input.

The following observations can be made from these waveforms:

- When the input signal is balanced, there is no double-frequency ripple
- When the input signal contains the negative sequence component, there is a double-frequency ripple with the peak-to-peak magnitude of about 120 MHz on the frequency and about 0.6◦ on the phase angle (as expected for the selection of ζ = 0.5 and ωn = 0.25ωo)
- It takes over a full cycle for the estimated output to reach the new steady state

The 3-phase PLL has a simple and robust structure and can track the frequency and angle changes smoothly. It does have error and a double-frequency ripple under unbalanced conditions.

A 3-phase grid-connected inverter shown below is presented here to illustrate how PLL is used in a practical application. Files of this example can be found in “examples\PLL Blocks\3-phase”.

The control is based on the dq frame. The 3-phase PLL block is used to generate the angle of the grid voltage. This angle is then used to convert the currents from the abc frame to the dq frame. PI controllers are used to control the currents. The system parameters and the design of the PI controllers as well as the PLL block are presented in the parameter file.

In this system, the operating conditions are changed as below:

- At t = 0.02 sec., the Iq reference is changed from 0 to 12
- At t = 0.06 sec., the Id reference is changed from 0 to 8
- At t = 0.1 sec., Phase a and b are shorted

Waveforms of the inverter system are shown below.

The top panel shows the inverter currents. The middle panel shows the grid voltages. The bottom panel shows the currents Id and Iq and their reference values. It can be observed that a fast and smooth response is achieved. Also, after 0.1 sec. when there is a short circuit, there is a significant amount of double-frequency ripple.

Similar test circuit and 3-phase inverter examples are provided for the discrete domain 3-phase PLL block, and the PSIM files can be found in “examples\Digital Control\PLL Blocks\3-phase”.

The 3-phase enhanced PLL block has the capability to handle general 3-phase signals, regardless if they are balanced or not. It is able to decompose the signals into positive, negative, and zero sequence components. Furthermore, it provides all the information regarding the input signals, including frequency, amplitude, and phase angle.

The enhanced PLL block does not cause any error in the presence of negative and zero sequence components. This feature makes it ideally suited for applications where various devices are connected to a distribution system causing unbalance conditions to occur.

A detailed discussion on the technical background of the enhanced 3-phase PLL block can be found in [3].

Two blocks for enhanced PLL, one in the continuous time domain and the other in the discrete time domain, are provided in PSIM as below:

The PLL block in the discrete domain (right) has the same image and terminal definition as the block in the continuous domain (left), except there, is a character “z” at the upper right corner.

**The PLL block parameters are:**

Proportional Gain *kp* = Proportional gain in the PLL circuit

Integral Gain* ki* = Integral gain in the PLL circuit

Rated Input = Frequency Rated frequency of the input, in Hz

Rated Input Amplitude (peak) = Rated input amplitude Ao (phase peak value)

Coefficient lambda = Coefficient λ

Sampling Frequency = Sampling frequency, in Hz (for the discrete domain block only)

1) Choose the first damping ratio ζ1.

The first damping ratio ζ1 determines the filtering strength of the ePLL. A smaller ζ1 means stronger filtering but a slower dynamic response. We suggest a value range below for typical power applications:

*0.25 ≤ ζ_1 ≤0 .75*

2) Choose the second damping ratio ζ2.

The second damping ratio corresponds to the damping ratio of the frequency loop. Since very fast frequency variation does not happen typically, can be set to a large value to avoid unnecessary oscillations. The recommended value range is:

*1 ≤ ζ_2 ≤ 2*

Calculate the parameters *kp* and *ki* as:

*k_p=ζ_1 ω_o*

*k_i=(k_p^2)/(4ζ_2^2 )*

3) Calculate the integrating gain *ki.*

The integrating gain *ki* may be made adaptive to further limit the range of frequency oscillations caused by phase angle jump or during the starting process [4]. With this approach, the ki equation is changed to:

This will limit the spurious frequency estimation swings caused by phase jump at the cost of reducing the actual frequency estimation speed. For typical applications, the suggested range of the constant λ is:

*0 ≤ λ ≤ 20*

This will give the desired trade-off. A larger value of λ means stronger suppression of the frequency swing. The default value is set to 10. If λ=0, this feature is disabled.

A simple circuit is built to test the basic operations of the 3-phase PLL block as shown below.

The 3-phase input signals consist of positive, negative, and zero sequence components generated by three subcircuits. The negative and zero sequence circuits use the phase angle from the positive sequence circuit to ensure the same frequency, and they also have their own initial phase shifts.

**The input signals have the following changes and disturbances:**

- Phase disturbance at t = 0.1 sec
- Frequency change at t = 0.3 sec
- Amplitude change at t = 0.4 sec
- Negative sequence component is applied at t = 0.5 sec
- Zero sequence component is applied at t = 0.6 sec

The waveforms are shown below.

The top panel shows the input signal *uabc(t)*. The upper middle panel shows the input *ua(t)* and the unitary synchronous output *y(t)*. The lower middle panel shows the input frequency and the estimated frequency. The bottom panel shows estimated positive, negative, and zero sequence component amplitudes.

The following observations can be made from these waveforms:

- When the input signal contains the negative sequence or zero sequence components, there is no double-frequency ripple
- The dynamic response is fast

The result confirms that the enhanced PLL block not only removes the double-frequency error under unbalanced conditions, but also provides additional information such as the magnitudes and phase angles of positive, negative, and zero sequence components.

A 3-phase grid-connected inverter shown below is presented here to illustrate how PLL is used in a practical application. Files of this example can be found in “examples\PLL Blocks\3-phase”.

The control is based on the dq frame. The 3-phase PLL block is used to generate the angle of the grid voltage. This angle is then used to convert the currents from the abc frame to the dq frame. PI controllers are used to control the currents. The system parameters and the design of the PI controllers as well as the PLL block are presented in the parameter file.

**In this system, the operating conditions are changed as below:**

- At t = 0.02 sec., the Iq reference is changed from 0 to 12
- At t = 0.06 sec., the Id reference is changed from 0 to 8
- At t = 0.1 sec., Phase a and b are shorted

Waveforms of the inverter system are shown below.

The top panel shows the inverter currents. The middle panel shows the grid voltages. The bottom panel shows the currents Id and Iq and their reference values. It can be observed that a fast and smooth response is achieved. Also, with the enhanced PLL, the inverter can continue to supply clean and balanced currents to the grid even under unbalanced conditions.

Similar test circuit and 3-phase inverter examples are provided for the discrete domain 3-phase PLL block, and the PSIM files can be found in “examples\Digital Control\PLL Blocks\3-phase”.

Induction furnace based on AC/DC and DC/AC conversion stages. The rectifier pulse generator contains a PLL to produce equidistant pulses for all six thyristors by means of single-phase synchronism. The PLL of the inverter generates the pulses to the IGBT’s according to the signal generated by the circuit or resonant load (RLC).

The figure shown is a general structure for the natural reference frame control strategy, where energy from a renewable energy source (DC Bus) can be delivered to the grid. The DC-link voltage controller is used for balancing the power flow in the system. The phase angle of the grid voltages is provided by a PLL. This estimate is required to create the three current references. Each value is compared with the corresponding current measurement. The generated error is the input to each hysteresis controller. The output of these blocks is the switching state for the devices in the power inverter. The inverter controller can be used to control the active and reactive energy generated to the grid, the dc-link voltage regulation, to ensure the high quality of the injected energy, and the grid synchronization.

**[1]** M Karimi-Ghartemani and MR Iravani, “A new phase-locked loop (pll) system”, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No. 01CH37257), volume 1, pages 421–424. IEEE, 2001.

**[2]** Masoud Karimi-Ghartemani and M Reza Iravani, “A nonlinear adaptive filter for online signal analysis in power systems: Applications”, IEEE Power Engineering Review, 22(1):72–72, 2002.

**[3]** Masoud Karimi-Ghartema, Enhanced Phase-Locked Loop Structures for Power and Energy Applications, John Wiley & Sons, 2014.

**[4]** Masoud Karimi Ghartemani, Sayed Ali Khajehoddin, Praveen K Jain, and Alireza Bakhshai, “Problems of startup and phase jumps in PLL systems”. IEEE Transactions on Power Electronics, 27(4):1830–1838, 2012.